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ltc3115-1 1 31151f typical application features description 40v, 2a synchronous buck-boost dc/dc converter the ltc ? 3115-1 is a high voltage monolithic synchronous buck-boost dc/dc converter. its wide 2.7v to 40v input and output voltage ranges make it well suited to a wide variety of automotive and industrial applications. a proprietary low noise switching algorithm optimizes efficiency with input voltages that are above, below or even equal to the output voltage and ensures seamless transitions between operational modes. programmable frequency pwm mode operation provides low noise, high efficiency operation and the ability to syn - chronize switching to an external clock. switching frequen - cies up to 2mhz are supported to allow use of small valued inductors for miniaturization of the application circuit. pin selectable burst mode operation reduces standby current and improves light load efficiency which combined with a 3a shutdown current make the ltc3115-1 ideally suited for battery-powered applications. additional features include output disconnect in shutdown, short-circuit protection and internal soft-start. the ltc3115-1 is available in ther - mally enhanced 16-lead 4mm 5mm 0.75mm dfn and 20 - lead tssop packages. efficiency vs v in applications n wide v in range: 2.7v to 40v n wide v out range: 2.7v to 40v n 1a output current for v in 3.6v, v out = 5v n 2a output current in step-down operation for v in 6v n programmable frequency: 100khz to 2mhz n synchronizable up to 2mhz with an external clock n up to 95% efficiency n 30a no-load quiescent current in burst mode ? operation n ultralow noise buck-boost pwm n internal soft-start n 3a supply current in shutdown n programmable input undervoltage lockout n small 4mm 5mm 0.75mm dfn package n thermally enhanced 20-lead tssop package n 24v/28v industrial applications n automotive power systems n telecom, servers and networking equipment n firewire regulator n multiple power source supplies l , lt, ltc, ltm, burst mode, ltspice, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6404251, 6166527 and others pending. bst1 bst2 pv in v in vc pv out pwm/sync fb run pv cc v cc rt sw1 sw2 gnd pgnd ltc3115-1 10h 0.1f burst pwm 2.7v to 40v 0.1f 33pf (optional) 5v 1a v in > 3.6v 2a v in 6v 4.7f 47f 1m 249k 4.7f 3115 ta01a 47.5k 15k 60.4k 3300pf off on input voltage (v) efficiency (%) 95 90 85 31151 ta01b 70 80 75 40 2 10 i load = 0.5a i load = 1a
ltc3115-1 2 31151f pin configuration absolute maximum ratings v in , pv in , pv out ........................................ C0.3v to 45v v sw1 dc ........................................... C0.3v to (pv in + 0.3v) pulsed (<100ns) ...................... C1.5v to (pv in + 1.5v) v sw2 dc ......................................... C0.3v to (pv out + 0.3v) pulsed (<100ns) .................... C1.5v to (pv out + 1.5v) v run ............................................. C0.3v to (v in + 0.3v) (note 1) order information lead free finish tape and reel part marking* package description temperature range ltc3115edhd-1#pbf ltc3115edhd-1#trpbf 31151 16-lead (5mm 4mm) plastic dfn C40c to 125c ltc3115idhd-1#pbf ltc3115idhd-1#trpbf 31151 16-lead (5mm 4mm) plastic dfn C40c to 125c ltc3115efe-1#pbf ltc3115efe-1#trpbf ltc3115fe-1 20-lead plastic tssop C40c to 125c ltc3115ife-1#pbf ltc3115ife-1#trpbf ltc3115fe-1 20-lead plastic tssop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ v bst1 ..................................... v sw1 C 0.3v to v sw1 + 6v v bst2 ..................................... v sw2 C 0.3v to v sw2 + 6v voltage, all other pins ................................. C0.3v to 6v operating junction temperature range (notes 2, 4) ltc3115e-1/ ltc3115i-1 ..................... C40c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) fe ...................................................................... 300c 16 15 14 13 12 11 10 9 pgnd 17 1 2 3 4 5 6 7 8 pwm/sync sw1 pv in bst1 bst2 pv cc v in v cc run sw2 pv out gnd gnd vc fb rt top view dhd package 16-lead (5mm 4mm) plastic dfn t jmax = 125c, ja = 43c/w, jc = 4.3c/w exposed pad (pin 17) is pgnd, must be soldered to pcb fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 pgnd run sw2 pv out gnd gnd vc fb rt pgnd pgnd pwm/sync sw1 pv in bst1 bst2 pv cc v in v cc pgnd 21 pgnd t jmax = 125c, ja = 38c/w, jc = 10c/w exposed pad (pin 21) is pgnd, must be soldered to pcb for rated thermal performance
ltc3115-1 3 31151f the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are for t a = 25c (note 2). v in = 24v, v out = 5v, unless otherwise noted. electrical characteristics parameter conditions min typ max units input operating voltage l 2.7 40 v output operating voltage l 2.7 40 v input undervoltage lockout threshold v in falling v in rising v in rising (0c to 125c) l l 2.4 2.6 2.7 2.8 2.725 v v v input undervoltage lockout hysteresis 100 mv v cc undervoltage lockout threshold v cc falling l 2.4 2.6 v v cc undervoltage lockout hysteresis 200 mv input current in shutdown v run = 0v 3 10 a input quiescent current in burst mode operation v fb = 1.1v (not switching) 50 a oscillator frequency r t = 35.7k l 900 1000 1100 khz oscillator operating frequency l 100 2000 khz pwm/sync clock input frequency l 100 2000 khz pwm/sync input logic threshold l 0.5 1.0 1.5 v soft-start duration 9 ms feedback voltage l 977 1000 1017 mv feedback voltage line regulation v in = 2.7v to 40v 0.1 % feedback pin input current 1 50 na run pin input logic threshold l 0.3 0.8 1.1 v run pin comparator threshold v run rising l 1.16 1.21 1.26 v run pin hysteresis current 500 na run pin hysteresis voltage 100 mv inductor current limit (note 3) l 2.4 3.0 3.7 a reverse inductor current limit current into pv out (note 3) 1.5 a burst mode inductor current limit (note 3) 0.65 1.0 1.35 a maximum duty cycle percentage of period sw2 is low in boost mode, r t = 35.7k (note 5) l 90 95 % minimum duty cycle percentage of period sw1 is high in buck mode, r t = 35.7k (note 5) l 0 % sw1, sw2 minimum low time r t = 35.7k (note 5) 100 ns n-channel switch resistance switch a (from pv in to sw1) switch b (from sw1 to pgnd) switch c (from sw2 to pgnd) switch d (from pv out to sw2) 150 150 150 150 m m m m n-channel switch leakage pv in = pv out = 40v 0.1 10 a pv cc /v cc external forcing voltage 4.58 5.5 v v cc regulation voltage i vcc = 1ma 4.33 4.45 4.58 v v cc load regulation i vcc = 1ma to 20ma 1.2 % v cc line regulation i vcc = 1ma, v in = 5v to 40v 0.5 % v cc current limit v cc = 2.5v 50 110 ma v cc dropout voltage i vcc = 5ma, v in = 2.7v 50 mv v cc reverse current v cc = 5v, v in = 3.6v 10 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3115-1 is tested under pulsed load conditions such that t j t a . the ltc3115e-1 is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are ensured by design, characterization and correlation with statistical process controls. the ltc3115i-1 specifications are guaranteed over the C40c to 125c operating junction temperature range. the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.
ltc3115-1 4 31151f typical performance characteristics pwm mode efficiency, v out = 5v, f sw = 1mhz, non-bootstrapped pwm mode efficiency, v out = 12v, f sw = 1mhz pwm mode efficiency, v out = 24v, f sw = 1mhz pwm mode efficiency, v out = 5v, f sw = 500khz, non-bootstrapped pwm mode efficiency, v out = 12v, f sw = 500khz pwm mode efficiency, v out = 24v, f sw = 500khz (t a = 25c unless otherwise specified) electrical characteristics the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the following formula: t j = t a + (p d ? ja ) where ja is the thermal impedance of the package. note 3: current measurements are performed when the ltc3115-1 is not switching. the current limit values measured in operation will be somewhat higher due to the propagation delay of the comparators. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 5: switch timing measurements are made in an open-loop test configuration. timing in the application may vary somewhat from these values due to differences in the switch pin voltage during the non-overlap durations when switch pin voltage is influenced by the magnitude and direction of the inductor current. load current (a) 0.01 60 efficiency (%) 80 100 0.10 1 31151 g01 40 50 70 90 30 20 v in = 3.6v v in = 5v v in = 12v v in = 24v v in = 36v load current (a) 0.01 70 efficiency (%) 80 90 100 0.1 1 31151 g02 60 50 40 30 v in = 5v v in = 12v v in = 24v v in = 36v load current (a) 0.01 70 efficiency (%) 80 90 0.1 1 31151 g03 60 30 50 40 100 v in = 12v v in = 18v v in = 24v v in = 36v load current (a) 0.01 60 efficiency (%) 80 100 0.1 1 31151 g04 40 50 70 90 30 20 v in = 3.6v v in = 5v v in = 12v v in = 24v v in = 36v load current (a) 0.01 70 efficiency (%) 80 90 100 0.1 1 31151 g05 60 50 40 30 v in = 5v v in = 12v v in = 24v v in = 36v load current (a) 0.01 70 efficiency (%) 80 90 0.1 1 31151 g06 60 30 40 50 100 v in = 12v v in = 18v v in = 24v v in = 36v
ltc3115-1 5 31151f burst mode efficiency, v out = 5v, l = 15h, non-bootstrapped burst mode efficiency, v out = 12v, l = 15h burst mode efficiency, v out = 24v, l = 15h typical performance characteristics (t a = 25c unless otherwise specified) maximum load current vs v in , burst mode operation burst mode no-load input current vs v in pwm mode no-load input current vs v in maximum load current vs v in , pwm mode maximum load current vs v in , pwm mode maximum load current vs v in , pwm mode load current (ma) 0.1 70 efficiency (%) 80 90 1 10 100 31151 g07 60 65 75 85 55 50 v in = 3.6v v in = 12v v in = 24v v in = 36v load current (ma) 0.1 70 efficiency (%) 80 95 90 1 10 100 31151 g08 60 65 75 85 55 50 v in = 5v v in = 12v v in = 24v v in = 36v load current (ma) 0.1 70 efficiency (%) 80 90 1 10 100 31151 g09 60 65 75 85 55 50 v in = 12v v in = 18v v in = 24v v in = 36v input voltage (v) 2 0 input current (a) 100 200 400 10 40 31151 g10 300 50 150 350 250 v out = 24v v out = 15v v out = 5v v out = 5v, bootstrapped input voltage (v) 2 0 input current (ma) 10 20 30 40 10 40 31151 g11 50 5 15 25 35 45 v out = 24v v out = 12v v out = 5v f sw = 1mhz input voltage (v) load current (a) 2.5 2.0 1.5 31151 g12 0 1.0 0.5 40 2 10 l = 22h f sw = 500khz v out = 24v v out = 12v v out = 5v input voltage (v) 2 10 10 load current (ma) 100 1000 40 31151 g13 l = 22h v out = 32v v out = 12v v out = 5v input voltage (v) load current (a) 2.5 2.0 1.5 31151 g47 0 1.0 0.5 40 2 10 l = 15h f sw = 1mhz v out = 24v v out = 12v v out = 5v input voltage (v) load current (a) 2.5 2.0 1.5 31151 g48 0 1.0 0.5 40 2 10 l = 5.2h f sw = 2mhz v out = 12v v out = 5v
ltc3115-1 6 31151f typical performance characteristics combined v cc /pv cc supply current vs v cc combined v cc /pv cc supply current vs temperature output voltage load regulation v cc regulator load regulation (t a = 25c unless otherwise specified) v cc regulator line regulation output voltage line regulation v cc voltage vs temperature v cc (v) 2.5 v cc /pv cc current (ma) 6 8 10 4 5 31151 g16 4 2 0 3 3.5 4.5 12 14 16 5.5 f sw = 1mhz f sw = 500khz temperature (c) ?50 11.0 v cc /pv cc current (ma) 11.1 11.3 11.4 11.5 12.0 11.7 0 50 31151 g17 11.2 11.8 11.9 11.6 100 150 v in = 6v v out = 5v f sw = 1mhz input voltage (v) 0 ?0.5 change in output voltage from v in = 20v (%) ?0.4 ?0.2 ?0.1 0 0.5 0.2 10 20 31151 g19 ?0.3 0.3 0.4 0.1 30 40 temperature (c) ?50 ?1.0 change from 25c (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 0 50 31151 g20 ?0.6 0.6 0.8 0.2 100 150 input voltage (v) 0 ?1.0 change from v in = 24v (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 10 20 31151 g22 ?0.6 0.6 0.8 0.2 30 40 load current (a) 0 ?0.5 change in voltage from zero load (%) ?0.4 ?0.2 ?0.1 0 0.5 0.2 0.5 1 31151 g18 ?0.3 0.3 0.4 0.1 1.5 2 i cc (ma) 0 change in voltage from i cc = 0ma (%) ?1.0 ?0.5 0 40 31151 g21 ?1.5 ?2.0 ?2.5 10 20 30 50 efficiency vs switching frequency combined v cc /pv cc supply current vs switching frequency switching frequency (khz) 0 efficiency (%) 80 85 2000 31151 g14 75 70 500 1000 1500 95 90 bootstrapped pwm mode l = 47h v in = 24v v out = 5v i load = 0.5a non-bootstrapped switching frequency (khz) 0 20 25 35 1500 31151 g15 15 10 500 1000 2000 5 0 30 v cc /pv cc current (ma) v in = 36v v out = 24v v in = 12v v out = 5v
ltc3115-1 7 31151f typical performance characteristics v cc regulator dropout voltage vs temperature run pin threshold vs temperature run pin hysteresis current vs temperature oscillator frequency vs r t oscillator frequency vs temperature (t a = 25c unless otherwise specified) power switch resistance vs temperature oscillator frequency vs v in run pin current vs run pin voltage shutdown current on v in /pv in vs input voltage temperature (c) ?50 dropout voltage (v) 0.10 0.15 150 31151 g23 0.05 0 0 50 100 0.25 0.20 v in = 4v i vcc = 20ma temperature (c) ?50 ?1.0 change from 25c (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 0 50 31151 g24 ?0.6 0.6 0.8 0.2 100 150 temperature (c) ?50 change from 25c (%) 0 0.5 1.0 150 31151 g25 ?0.5 ?1.0 ?2.0 0 50 100 ?1.5 2.0 1.5 r t (k) 10 100 switching frequency (khz) 1000 10000 100 1000 31151 g26 temperature (c) ?50 change from 25c (%) 0 0.5 1.0 150 31151 g27 ?0.5 ?1.0 ?2.0 0 50 100 ?1.5 2.0 1.5 f sw = 1mhz v in (v) 2 ?2.0 change from v in = 24v (%) ?1.0 0 2.0 10 40 31151 g28 1.0 ?1.5 ?0.5 1.5 0.5 f sw = 1mhz run pin voltage (v) 0 current into run pin (a) 3 4 5 40 31151 g29 2 1 ?1 10 20 30 0 7 v in = 40v 6 input voltage (v) 0 0 combined v in /pv in current (a) 0.5 1.0 1.5 2.0 2.5 3.0 v run = 0v 10 20 30 40 31151 g30 temperature (c) ?50 0 power switch (a-d) resistance (m) 50 100 150 200 250 300 0 50 100 150 31151 g31
ltc3115-1 8 31151f typical performance characteristics inductor current limit thresholds vs temperature (t a = 25c unless otherwise specified) sw1, sw2 minimum low time vs v cc sw1, sw2 minimum low time vs switching frequency sw2 maximum duty cycle vs switching frequency die temperature rise vs load current, v out = 5v, f sw = 750khz die temperature rise vs load current, v out = 5v, f sw = 1.5mhz sw1, sw2 minimum low time vs temperature temperature (c) ?50 ?5 change from 25c (%) ?4 ?2 ?1 0 5 2 0 50 31151 g34 ?3 3 4 1 100 150 swa current limit swb current limit temperature (c) ?50 90 minimum low time (ns) 92 96 98 100 110 104 0 50 31151 g35 94 106 108 102 100 150 f sw = 1mhz no load v cc (v) 2.5 60 minimum low time (ns) 80 100 120 140 180 3 3.5 4 4.5 31151 g36 5 5.5 160 f sw = 300khz f sw = 1mhz f sw = 2mhz switching frequency (khz) 0 140 160 200 1500 31151 g37 120 100 500 1000 2000 80 60 180 minimum low time (ns) v cc = 2.7v v cc = 4.4v switching frequency (khz) 0 maximum duty cycle (%) 92 93 2000 31151 g38 91 90 500 1000 1500 95 94 power switch resistance vs v cc fb voltage vs temperature v cc (v) 2.5 140 power switch (a-d) resistance (m) 145 150 155 160 170 3 3.5 4 4.5 31151 g32 5 5.5 165 temperature (c) ?50 ?1.0 change from 25c (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 0 50 31151 g33 ?0.6 0.6 0.8 0.2 100 150 load current (a) 0 0 die temperature change from ambient (c) 10 20 30 40 50 60 0.5 1 1.5 2 31151 g49 v in = 36v v in = 24v v in = 12v v in = 6v v in = 3.6v standard demo pcb l = 15h mss1048 load current (a) 0 0 die temperature change from ambient (c) 10 20 30 50 70 100 90 40 60 80 0.5 1 1.5 2 31151 g50 v in = 36v v in = 24v v in = 12v v in = 6v v in = 3.6v standard demo pcb l = 15h mss1048
ltc3115-1 9 31151f typical performance characteristics die temperature rise vs load current, v out = 12v, f sw = 750khz load transient (0a to 1a), v in = 24v, v out = 5v load transient (0a to 1a), v in = 3.6v, v out = 5v output voltage ripple in burst mode operation, v in = 24v, v out = 5v (t a = 25c unless otherwise specified) phase-locked loop acquisition, v in = 24v 1.2mhz clock phase-locked loop release, v in = 24v, 1.2mhz clock soft-start waveforms burst mode operation to pwm mode output voltage transient output voltage ripple in pwm mode, v in = 24v, v out = 5v v out (200mv/div) load current (1a/div) front page application 200s/div 31151 g39 inductor current (1a/div) v out (200mv/div) load current (1a/div) front page application 200s/div 31151 g40 inductor current (2a/div) v out (50mv/div) l = 15h c out = 22f i load = 25ma 20s/div 31151 g41 inductor current (0.5a/div) v out (5mv/div) l = 22h c out = 22f i load = 2a f sw = 750khz 1s/div 31151 g43 inductor current (100ma/div) v pwm/sync (5v/div) v out (200mv/div) front page application 50s/div 31151 g45 inductor current (1a/div) v pwm/sync (5v/div) v out (200mv/div) front page application 50s/div 31151 g46 inductor current (1a/div) v out (2v/div) v run (5v/div) v cc (2v/div) front page application 2ms/div 31151 g42 inductor current (1a/div) v out (200mv/div) v pwm/sync (5v/div) front page application 500s/div 31151 g44 inductor current (1a/div) load current (a) 0 0 die temperature change from ambient (c) 10 20 30 50 70 80 40 60 0.5 1 1.5 2 31151 g51 v in = 36v v in = 24v v in = 12v v in = 6v standard demo pcb l = 15h mss1048
ltc3115-1 10 31151f pin functions (dhd/fe) run (pin 1/pin 2): input to enable and disable the ic and set custom input uvlo thresholds. the run pin can be driven by an external logic signal to enable and disable the ic. in addition, the voltage on this pin can be set by a resistor divider connected to the input voltage in order to provide an accurate undervoltage lockout threshold. the ic is enabled if run exceeds 1.21v nominally. once enabled, a 0.5a current is sourced by the run pin to provide hysteresis. to continuously enable the ic, this pin can be tied directly to the input voltage. the run pin cannot be forced more than 0.3v above v in under any condition. sw2 (pin 2/pin 3): buck-boost converter power switch pin. this pin should be connected to one side of the buck- boost inductor. pv out (pin 3/pin 4): buck-boost converter power output. this pin should be connected to a low esr capacitor with a value of at least 10f. the capacitor should be placed as close to the ic as possible and should have a short return path to ground. in applications with v out > 20v that are subject to output overload or short-circuit conditions, it is recommended that a schottky diode be installed from sw2 (anode) to pv out (cathode). in applications subject to output short circuits through an inductive load, it is rec - ommended that a schottky diode be installed from ground (anode) to pv out (cathode) to limit the extent that pv out is driven below ground during the short-circuit transient. gnd (pins 4, 5/pins 5, 6): signal ground. these pins are the ground connections for the control circuitry of the ic and must be tied to ground in the application. vc (pin 6/pin 7): error amplifier output. a frequency compensation network must be connected between this pin and fb to stabilize the voltage control loop. fb (pin 7/pin 8): feedback voltage input. a resistor divider connected to this pin sets the output voltage for the buck- boost converter. the nominal fb voltage is 1000mv. care should be taken in the routing of connections to this pin in order to minimize stray coupling to the switch pin traces. rt (pin 8/pin 9): oscillator frequency programming pin. a resistor placed between this pin and ground sets the switching frequency of the buck-boost converter. v cc (pin 9/pin 12): low voltage supply input for ic con - trol circuitry. this pin powers internal ic control circuitry and must be connected to the pv cc pin in the application. a 4.7f or larger bypass capacitor should be connected between this pin and ground. the v cc and pv cc pins must be connected together in the application. v in (pin 10/pin 13): power supply connection for internal circuitry and the v cc regulator. this pin provides power to the internal v cc regulator and is the input voltage sense connection for the v in divider. a 0.1f bypass capacitor should be connected between this pin and ground. the bypass capacitor should be located as close to the ic as possible and should have a short return path to ground. pv cc (pin 11/pin 14): internal v cc regulator output. this pin is the output pin of the internal linear regulator that generates the v cc rail from v in . the pv cc pin is also the supply connection for the power switch gate drivers. if the trace connecting pv cc to v cc cannot be made short in length, an additional bypass capacitor should be connected between this pin and ground. the v cc and pv cc pins must be connected together in the application. bst2 (pin 12/pin 15): flying capacitor pin for sw2. this pin must be connected to sw2 through a 0.1f capacitor. this pin is used to generate the gate drive rail for power switch d. bst1 (pin 13/pin 16): flying capacitor pin for sw1. this pin must be connected to sw1 through a 0.1f capacitor. this pin is used to generate the gate drive rail for power switch a. pv in (pin 14/pin 17): power input for the buck-boost converter. a 4.7f or larger bypass capacitor should be connected between this pin and ground. the bypass capacitor should be located as close to the ic as possible and should via directly down to the ground plane. when powered through long leads or from a high esr power source, a larger bulk input capacitor (typically 47f to 100f) may be required. sw1 (pin 15/pin 18): buck-boost converter power switch pin. this pin should be connected to one side of the buck- boost inductor.
ltc3115-1 11 31151f pin functions (dhd/fe) pwm/sync (pin 16/pin 19): burst mode/pwm mode control pin and synchronization input. forcing this pin high causes the ic to operate in fixed frequency pwm mode at all loads using the internal oscillator at the frequency set by the rt pin. forcing this pin low places the ic into burst mode operation for improved efficiency at light load and reduced standby current. if an external clock signal is connected to this pin, the buck-boost converter will synchronize its switching with the external clock using fixed frequency pwm mode operation. the pulse width (negative or positive) of the applied clock should be at least 100ns. pgnd (exposed pad pin 17/pins 1, 10, 11, 20, ex - posed pad pin 21): power ground connections. these pins should be connected to the power ground in the application. the exposed pad in the dhd package is the power ground connection. it must be soldered to the pcb and electrically connected to ground through the shortest and lowest impedance connection possible. for optimal thermal performance, the exposed pad should be connected to the pcb ground plane in both the dhd and fe packages. block diagram pin numbers are shown for the dhd package only. current limit + ? 3a d a pgnd cb pv out reverse current limit + ? ?1.5a zero current + ? 0a 3 v in pv cc * 10 11 bst2 12 bst1 13 v cc * v cc v in v in 2.4v 0.5a 9 sw2 2 gate drives pgnd soft-start ramp 1000mv sw1 15 pv in 14 fb 7 vc reverse blocking ldo bandgap reference overtemperature oscillator mode selection 1000mv 1.21v pwm chip enable exposed pad burst /pwm (pwm mode if pwm/sync is high or switching) v in + + ? 6 rt 8 pwm/sync *pv cc and v cc must be connected together in the application the exposed pad is an electrical connection and must be soldered to the board and electrically connected to ground 16 input uvlo + ? 1.21v pgnd gnd + ? 2.4v v cc uvlo + ? run 3115 bd 1 17 4 gnd 5
ltc3115-1 12 31151f operation introduction the ltc3115-1 is a monolithic buck-boost converter that can operate with input and output voltages from as low as 2.7v to as high as 40v. four internal low resistance n- channel dmos switches minimize the size of the application circuit and reduce power losses to maximize efficiency. internal high side gate drivers, which require only the addition of two small external capacitors, further simplify the design process. a proprietary switch control algorithm allows the buck-boost converter to maintain output volt- age regulation with input voltages that are above, below or equal to the output voltage. transitions between these operating modes are seamless and free of transients and subharmonic switching. the ltc3115-1 can be configured to operate over a wide range of switching frequencies, from 100khz to 2mhz, allowing applications to be optimized for board area and efficiency. with its configurability and wide operating voltage range, the ltc3115-1 is ideally suited to a wide range of power systems especially those requiring compatibility with a variety of input power sources such as lead-acid batteries, usb ports, and industrial supply rails as well as from power sources which have wide or poorly controlled voltage ranges such as firewire and unregulated wall adapters. the ltc3115-1 has an internal fixed-frequency oscillator with a switching frequency that is easily set by a single external resistor. in noise sensitive applications, the con - verter can also be synchronized to an external clock via the pwm/sync pin. the ltc3115-1 has been optimized to reduce input current in shutdown and standby for ap- plications which are sensitive to quiescent current draw, such as battery-powered devices. in burst mode opera - tion, the no-load standby current is only 50a (typical) and in shutdown the total supply current is reduced to 3a (typical). pwm mode operation with the pwm/sync pin forced high or driven by an ex - ternal clock, the ltc3115-1 operates in a fixed-frequency pulse width modulation (pwm) mode using a voltage mode control loop. this mode of operation maximizes the output current that can be delivered by the converter, reduces output voltage ripple, and yields a low noise fixed-frequency switching spectrum. a proprietary switching algorithm provides seamless transitions between operating modes and eliminates discontinuities in the average inductor cur - rent, inductor current ripple, and loop transfer function throughout all regions of operation. these advantages result in increased efficiency, improved loop stability, and lower output voltage ripple in comparison to the traditional 4-switch buck-boost converter. figure 1 shows the topology of the ltc3115-1 power stage which is comprised of four n-channel dmos switches and their associated gate drivers. in pwm mode operation both switch pins transition on every cycle independent of the input and output voltage. in response to the error ampli - fier output, an internal pulse width modulator generates the appropriate switch duty cycles to maintain regulation of the output voltage. when stepping down from a high input voltage to a lower output voltage, the converter operates in buck mode and switch d remains on for the entire switching cycle except for the minimum switch low duration (typically 100ns). during the switch low duration switch c is turned on which forces sw2 low and charges the flying capacitor, c bst2 , to ensure that the voltage of the switch d gate driver supply rail is maintained. the duty cycle of switches a and b are adjusted to provide the appropriate buck mode duty cycle. if the input voltage is lower than the output voltage, the converter operates in boost mode. switch a remains on for the entire switching cycle except for the minimum switch low duration (typically 100ns) while switches c and d are modulated to maintain the required boost mode figure 1. power stage schematic a pv cc bst1 c bst1 c bst2 l bst2 pv in pv out sw1 sw2 pv cc pv cc pv cc ltc3115-1 pgnd pgnd 31151 f01 b d c
ltc3115-1 13 31151f operation duty cycle. the minimum switch low duration ensures that flying capacitor c bst1 is charged sufficiently to maintain the voltage on the bst1 rail. oscillator and phase-locked loop the ltc3115-1 operates from an internal oscillator with a switching frequency that is configured by a single external resistor between the rt pin and ground. for noise sensi - tive applications, an internal phase-locked loop allows the ltc3115-1 to be synchronized to an external clock signal applied to the pwm/sync pin. the phase-locked loop is only able to increase the frequency of the internal oscillator to obtain synchronization. therefore, the r t resistor must be chosen to program the internal oscilla - tor to a lower frequency than the frequency of the clock applied to the pwm/sync pin. sufficient margin must be included to account for the frequency variation of the external synchronization clock as well as the worst-case variation in frequency of the internal oscillator. whether operating from its internal oscillator or synchronized to an external clock signal, the ltc3115-1 is able to operate with a switching frequency from 100khz to 2mhz, providing the ability to minimize the size of the external components and optimize the power conversion efficiency. error amplifier and v in divider the ltc3115-1 has an internal high gain operational amplifier which provides frequency compensation of the control loop that maintains output voltage regulation. to ensure stability of this control loop, an external compensa - tion network must be installed in the application circuit. a type iii compensation network as shown in figure 2 is recommended for most applications since it provides the flexibility to optimize the converters transient response while simultaneously minimizing any dc error in the output voltage. as shown in figure 2, the error amplifier is followed by an internal analog divider which adjusts the loop gain by the reciprocal of the input voltage in order to minimize loop-gain variation over changes in the input voltage. this simplifies design of the compensation network and optimizes the transient response over the entire range of input voltages. details on designing the compensation network in ltc3115-1 applications can be found in the applications information section of this data sheet. inductor current limits the ltc3115-1 has two current limit circuits that are designed to limit the peak inductor current to ensure that the switch currents remain within the capabilities of the ic during output short-circuit or overload conditions. the primary inductor current limit operates by injecting a current into the feedback pin which is proportional to the extent that the inductor current exceeds the current limit threshold (typically 3a). due to the high gain of the feedback loop, this injected current forces the error amplifier output to decrease until the average current through the inductor is approximately reduced to the current limit threshold. this current limit circuit maintains the error amplifier in an active state to ensure a smooth recovery and minimal overshoot once the current limit fault condition is removed. however, the reaction speed of this current limit circuit is limited by the dynamics of the error amplifier. on a hard output short, it is possible for the inductor current to increase substantially beyond the current limit threshold before the average current limit has time to react and reduce the inductor current. for this reason, there is a second current limit circuit which turns off power switch a if the current through switch a exceeds approximately 160% of the primary inductor current limit threshold. this provides additional protection in the case of an instantaneous hard output short and provides time for the primary current limit to react. in addition, if v out falls below 1.85v, the inductor current limit is folded back to half its nominal value in order to minimize power dissipation. figure 2. error amplifier and compensation network + ? 1000mv 31151 f02 ltc3115-1 v in vc c fb c pole r fb fb r ff v out r top r bot c ff pwm
ltc3115-1 14 31151f operation reverse current limit in pwm mode operation, the ltc3115-1 synchronously switches all four power devices. as a result, in addition to being able to supply current to the output, the converter has the ability to actively conduct current away from the output if that is necessary to maintain regulation. if the output is held above regulation, this could result in large reverse currents. this situation can occur if the output of the ltc3115-1 is held up momentarily by another supply as may occur during a power-up or power-down sequence. to prevent damage to the part under such conditions, the ltc3115-1 has a reverse current comparator that monitors the current entering power switch d from the load. if this current exceeds 1.5a (typical) switch d is turned off for the remainder of the switching cycle in order to prevent the reverse inductor current from reaching unsafe levels. output current capability the maximum output current that can be delivered by the ltc3115-1 is dependent upon many factors, the most significant being the input and output voltages. for v out = 5v and v in 3.6v, the ltc3115-1 is able to support up to a 1a load continuously. for v out = 12v and v in 12v, the ltc3115-1 is able to support up to a 2a load continu - ously. typically, the output current capability is greatest when the input voltage is approximately equal to the output voltage. at larger step-up voltage ratios, the output cur - rent capability is reduced because the lower duty cycle of switch d results in a larger inductor current being needed to support a given load. additionally, the output current capability generally decreases at large step-down voltage ratios due to higher inductor current ripple which reduces the maximum attainable inductor current. the output current capability can also be affected by inductor characteristics. an inductor with large dc resis - tance will degrade output current capability, particularly in boost mode operation. larger value inductors generally maximize output current capability by reducing inductor current ripple. in addition, higher switching frequencies (especially above 750khz) will reduce the maximum output current that can be supplied (see the typical performance characteristics for details). burst mode operation when the pwm/sync pin is held low, the buck-boost converter employs burst mode operation using a vari - able frequency switching algorithm that minimizes the no-load input quiescent current and improves efficiency at light load by reducing the amount of switching to the minimum level required to support the load. the output current capability in burst mode operation is substantially lower than in pwm mode and is intended to support light standby loads (typically under 50ma). curves showing the maximum burst mode load current as a function of the input and output voltage can be found in the typical characteristics section of this data sheet. if the converter load in burst mode operation exceeds the maximum burst mode current capability, the output will lose regulation. each burst mode cycle is initiated when switches a and c turn on producing a linearly increasing current through the inductor. when the inductor current reaches the burst mode current limit (1a typically) switches b and d are turned on, discharging the energy stored in the inductor into the output capacitor and load. once the inductor current reaches zero, all switches are turned off and the cycle is complete. current pulses generated in this manner are repeated as often as necessary to maintain regulation of the output voltage. in burst mode operation, the error amplifier is not used but is instead placed in a low current standby mode to reduce supply current and improve light load efficiency. soft-start to minimize input current transients on power-up, the ltc3115-1 incorporates an internal soft-start circuit with a nominal duration of 9ms. the soft-start is implemented by a linearly increasing ramp of the error amplifier refer - ence voltage during the soft-start duration. as a result, the duration of the soft-start period is largely unaffected by the size of the output capacitor or the output regula - tion voltage. given the closed-loop nature of the soft-start implementation, the converter is able to respond to load transients that occur during the soft-start interval. the soft-start period is reset by thermal shutdown and uvlo events on both v in and v cc .
ltc3115-1 15 31151f operation v cc regulator an internal low dropout regulator generates the 4.45v (nominal) v cc rail from v in . the v cc rail powers the in - ternal control circuitry and power device gate drivers of the ltc3115-1. the v cc regulator is disabled in shutdown to reduce quiescent current and is enabled by forcing the run pin above its logic threshold. the v cc regulator in - cludes current limit protection to safeguard against short circuiting of the v cc rail. for applications where the output voltage is set to 5v, the v cc rail can be driven from the output rail through a schottky diode. bootstrapping in this manner can provide a significant efficiency improvement, particularly at large voltage step down ratios, and may also allow operation down to a lower input voltage. the maximum operating voltage for the v cc pin is 5.5v. when forcing v cc externally, care must be taken to ensure that this limit is not exceeded. undervoltage lockout to eliminate erratic behavior when the input voltage is too low to ensure proper operation, the ltc3115-1 incor - porates internal undervoltage lockout (uvlo) circuitry. there are two uvlo comparators, one that monitors v in and another that monitors v cc . the buck-boost converter is disabled if either v in or v cc falls below its respective uvlo threshold. the input voltage uvlo comparator has a falling threshold of 2.4v (typical). if the input voltage falls below this level all switching is disabled until the input voltage rises above 2.6v (nominal). the v cc uvlo has a falling threshold of 2.4v. if v cc falls below this threshold the buck-boost converter is prevented from switching until v cc rises above 2.6v. depending on the particular application circuit it is pos - sible that either of these uvlo thresholds could be the factor limiting the minimum input operating voltage of the ltc3115-1. the dominant factor depends on the voltage drop between v in and v cc which is determined by the dropout voltage of the v cc regulator and is proportional to the total load current drawn from v cc . the load cur - rent on the v cc regulator is principally generated by the gate driver supply currents which are proportional to operating frequency and generally increase with larger input and output voltages. as a result, at higher switching frequencies and higher input and output voltages the v cc regulator dropout voltage will increase, making it more likely that the v cc uvlo threshold could become the limiting factor. curves provided in the typical perfor - mance characteristics section of this data sheet show the typical v cc current and can be used to estimate the v cc regulator dropout voltage in a particular application. in applications where v cc is bootstrapped (powered by v out or by an auxiliary supply rail through a schottky diode) the minimum input operating voltage will be limited only by the input voltage uvlo threshold. run pin comparator in addition to serving as a logic-level input to enable the ic, the run pin features an accurate internal compara - tor allowing it to be used to set custom rising and falling input undervoltage lockout thresholds with the addition of an external resistor divider. when the run pin is driven above its logic threshold (typically 0.8v) the v cc regulator is enabled which provides power to the internal control circuitry of the ic and the accurate run pin comparator is enabled. if the run pin voltage is increased further so that it exceeds the run comparator threshold (1.21v nominal), the buck-boost converter will be enabled. if the run pin is brought below the run comparator threshold, the buck-boost converter will inhibit switching, but the v cc regulator and control circuitry will remain powered unless the run pin is brought below its logic threshold. therefore, in order to place the part in shut - down and reduce the input current to its minimum level (3a typical) it is necessary to ensure that the run pin is brought below the worst-case logic threshold (0.3v). the run pin is a high voltage input and can be connected directly to v in to continuously enable the part when the input supply is present. if the run pin is forced above approximately 5v it will sink a small current as given by the following equation: i run ? v run ? 5v 5m ? with the addition of an external resistor divider as shown in figure 3, the run pin can be used to establish a custom
ltc3115-1 16 31151f operation input undervoltage lockout threshold. the buck-boost con - verter is enabled when the run pin reaches 1.21v which allows the rising uvlo threshold to be set via the resis - tor divider ratio. once the run pin reaches the threshold voltage, the comparator switches and the buck-boost converter is enabled. in addition, an internal 0.5a (typi - cal) current source is enabled which sources current out of the run pin raising the run pin voltage away from the threshold. in order to disable the part, v in must be reduced sufficiently to overcome the hysteresis generated by this current as well as the 100mv hysteresis of the run comparator. as a result, the amount of hysteresis can be independently programmed without affecting the rising uvlo threshold by scaling the values of both resistors. thermal considerations the power switches in the ltc3115-1 are designed to op - erate continuously with currents up to the internal current limit thresholds. however, when operating at high current levels there may be significant heat generated within the ic. in addition, in many applications the v cc regulator is operated with large input-to-output voltage differentials resulting in significant levels of power dissipation in its pass element which can add significantly to the total power dissipated within the ic. as a result, careful consideration must be given to the thermal environment of the ic in order to optimize efficiency and ensure that the ltc3115-1 is able to provide its full-rated output current. specifically, the exposed die attach pad of both the dhd and fe pack - ages should be soldered to the pc board and the pc board should be designed to maximize the conduction of heat out of the ic package. this can be accomplished by utilizing multiple vias from the die attach pad connection to other pcb layers containing a large area of exposed copper. if the die temperature exceeds approximately 165c, the ic will enter overtemperature shutdown and all switching will be inhibited. the part will remain disabled until the die cools by approximately 10c. the soft-start circuit is re-initialized in overtemperature shutdown to provide a smooth recovery when the fault condition is removed. figure 3. accurate run pin comparator 1.21v 0.8v v cc v in 0.5a ltc3115-1 ena 31151 f03 run r1 r2 enable switching input logic threshold enable v cc regulator and control circuits + ? + ?
ltc3115-1 17 31151f applications information the standard ltc3115-1 application circuit is shown as the typical application on the front page of this data sheet. the appropriate selection of external components is dependent upon the required performance of the ic in each particular application given considerations and trade-offs such as pcb area, cost, output and input voltage, allowable ripple voltage, efficiency and thermal considerations. this section of the data sheet provides some basic guidelines and con- siderations to aid in the selection of external components and the design of the application circuit. v cc capacitor selection the v cc output on the ltc3115-1 is generated from the input voltage by an internal low dropout regulator. the v cc regulator has been designed for stable operation with a wide range of output capacitors. for most applications, a low esr ceramic capacitor of at least 4.7f should be utilized. the capacitor should be placed as close to the pin as possible and should connect to the pv cc pin and ground through the shortest traces possible. the pv cc pin is the regulator output and is also the internal supply pin for the gate drivers and boost rail charging diodes. the v cc pin is the supply connection for the remainder of the control circuitry. the pv cc and v cc pins must be connected together on the application pcb. if the trace connecting v cc to pv cc cannot be made via a short con - nection, an additional 0.1f bypass capacitor should be placed between the v cc pin and ground using the shortest connections possible. inductor selection the choice of inductor used in ltc3115-1 application circuits influences the maximum deliverable output cur - rent, the magnitude of the inductor current ripple, and the power conversion efficiency. the inductor must have low dc series resistance or output current capability and efficiency will be compromised. larger inductance values reduce inductor current ripple and will therefore gener - ally yield greater output current capability. for a fixed dc resistance, a larger value of inductance will yield higher efficiency by reducing the peak current to be closer to the average output current and therefore minimize resistive losses due to high rms currents. however, a larger induc - tor value within any given inductor family will generally have a greater series resistance, thereby counteracting this efficiency advantage. in general, inductors with larger inductance values and lower dc resistance will increase the deliverable output current and improve the efficiency of ltc3115-1 applications. an inductor used in ltc3115-1 applications should have a saturation current rating that is greater than the worst-case average inductor current plus half the ripple current. the peak-to-peak inductor current ripple for each operational mode can be calculated from the following formula, where f is the switching frequency, l is the inductance, and t low is the switch pin minimum low time. the switch pin minimum low time can be determined from curves given in the typical performance characteristics section of this data sheet. ? i l(p-p)(buck) = v out l v in ? v out v in ? ? ? ? ? ? 1 f ? t low ? ? ? ? ? ? ? i l(p-p)(boost ) = v in l v out ? v in v out ? ? ? ? ? ? 1 f ? t low ? ? ? ? ? ? in addition to its influence on power conversion efficiency, the inductor dc resistance can also impact the maximum output current capability of the buck-boost converter par - ticularly at low input voltages. in buck mode, the output current of the buck-boost converter is generally limited only by the inductor current reaching the current limit threshold. however, in boost mode, especially at large step-up ratios, the output current capability can also be limited by the total resistive losses in the power stage. these include switch resistances, inductor resistance, and pcb trace resistance. use of an inductor with high dc resistance can degrade the output current capability from that shown in the typical performance characteristics sec - tion of this data sheet. as a guideline, in most applications the inductor dc resistance should be significantly smaller than the typical power switch resistance of 150m. different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. the choice of inductor style depends upon the price, sizing, and emi requirements of a particular application. table 1
ltc3115-1 18 31151f applications information provides a small sampling of inductors that are well suited to many ltc3115-1 applications. in applications with v out 20v, it is recommended that a minimum inductance value, l min , be utilized where f is the switching frequency: l min = 12h f / hz ( ) table 1. representative surface mount inductors part number value (h) dcr (m) max dc current (a) size (mm) w l h coilcraft lps6225 lps6235 mss1038 d03316p 4.7 6.8 22 15 65 75 70 50 3.2 2.8 3.3 3.0 6.2 6.2 2.5 6.2 6.2 3.5 10.2 10.5 3.8 12.9 9.4 5.2 cooper-bussmann cd1-150-r dr1030-100-r fp3-8r2-r dr1040-220-r 15 10 8.2 22 50 40 74 54 3.6 3.18 3.4 2.9 10.5 10.4 4.0 10.3 10.5 3.0 7.3 6.7 3.0 10.3 10.5 4.0 panasonic ellctv180m ellatv100m 18 10 30 23 3.0 3.3 12 12 4.2 10 10 4.2 sumida cdrh8d28/hp cdr10d48mnnp cdrh8d28np 10 39 4.7 78 105 24.7 3.0 3.0 3.4 8.3 8.3 3 10.3 10.3 5 8.3 8.3 3 taiyo-yuden nr10050t150m 15 46 3.6 9.8 9.8 5 toko b1047as-6r8n b1179bs-150m 892nas-180m 6.8 15 18 36 56 42 2.9 3.3 3.0 7.6 7.6 5 10.3 10.3 4 12.3 12.3 4.5 wrth 7447789004 744771133 744066150 4.7 33 15 33 49 40 2.9 2.7 3.2 7.3 7.3 3.2 12 12 6 10 10 3.8 capacitance, t low is the switch pin minimum low time, and i load is the output current. curves for the value of t low as a function of switching frequency and temperature can be found in typical performance characteristics section of this data sheet. ? v p-p(buck) = i load t low c out ? v p-p(boost) = i load fc out v out ? v in + t low fv in v out ? ? ? ? ? ? the output voltage ripple increases with load current and is generally higher in boost mode than in buck mode. these expressions only take into account the output voltage ripple that results from the output current being discontinuous. they provide a good approximation to the ripple at any significant load current but underestimate the output volt - age ripple at very light loads where output voltage ripple is dominated by the inductor current ripple. in addition to output voltage ripple generated across the output capacitance, there is also output voltage ripple produced across the internal resistance of the output capacitor. the esr-generated output voltage ripple is proportional to the series resistance of the output capacitor and is given by the following expressions where r esr is the series resistance of the output capacitor and all other terms are as previously defined. ? v p-p(buck) = i load r esr 1? t low f ? i load r esr ? v p-p(boost) = i load r esr v out v in 1? t low f ( ) ? i load r esr v out v in ? ? ? ? ? ? input capacitor selection the pv in pin carries the full inductor current and provides power to internal control circuits in the ic. to minimize input voltage ripple and ensure proper operation of the ic, a low esr bypass capacitor with a value of at least 4.7f should be located as close to this pin as possible. the traces connecting this capacitor to pv in and the ground plane should be made as short as possible. the v in pin provides power to the v cc regulator and other internal circuitry. if the pcb trace connecting v in to pv in is long, it output capacitor selection a low esr output capacitor should be utilized at the buck- boost converter output in order to minimize output voltage ripple. multilayer ceramic capacitors are an excellent option as they have low esr and are available in small footprints. the capacitor value should be chosen large enough to reduce the output voltage ripple to acceptable levels. neglecting the capacitor esr and esl, the peak-to-peak output voltage ripple can be calculated by the following formulas, where f is the switching frequency, c out is the
ltc3115-1 19 31151f applications information may be necessary to add an additional small value bypass capacitor near the v in pin. when powered through long leads or from a high esr power source, a larger value bulk input capacitor may be required. in such applications, a 47f to 100f electrolytic capacitor in parallel with a 1f ceramic capacitor generally yields a high performance, low cost solution. recommended input and output capacitors the capacitors used to filter the input and output of the ltc3115-1 must have low esr and must be rated to handle the large ac currents generated by switching con - verters. this is important to maintain proper functioning of the ic and to reduce output voltage ripple. there are many capacitor types that are well suited to such appli - cations including multilayer ceramic, low esr tantalum, os-con and poscap technologies. in addition, there are certain types of electrolytic capacitors such as solid aluminum organic polymer capacitors that are designed for low esr and high ac currents and these are also well suited to ltc3115-1 applications (table 2). the choice of capacitor technology is primarily dictated by a trade-off between cost, size and leakage current. notice that some capacitors such as the os-con and poscap technologies can exhibit significant dc leakage currents which may limit their applicability in devices which require low no-load quiescent current in burst mode operation. ceramic capacitors are often utilized in switching con - verter applications due to their small size, low esr, and low leakage currents. however, many ceramic capacitors designed for power applications experience significant loss in capacitance from their rated value with increased dc bias voltages. for example, it is not uncommon for a small surface mount ceramic capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. as a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a higher voltage rating than required in order to actually realize the intended capacitance at the full operating voltage. to ensure that the intended capacitance is realized in the application circuit, be sure to consult the capacitor vendors curve of capacitance versus dc bias voltage. table 2. representative bypass and output capacitors manufacturer, part number value (f) voltage (v) size l w h (mm), type, esr avx 12103d226mat2a 22 25 3.2 2.5 2.79 x5r ceramic tpme226k050r0075 22 50 7.3 4.3 4.1 tantalum, 75m kemet c2220x226k3ractu 22 25 5.7 5.0 2.4 x7r ceramic a700d226m016ate030 22 16 7.3 4.3 2.8 alum. polymer, 30m murata grm32er71e226ke15l 22 25 3.2 2.5 2.5 x7r ceramic nichicon plv1e121mdl1 82 25 8 8 12 alum. polymer, 25m panasonic ecj-4yb1e226m 22 25 3.2 2.5 2.5 x5r ceramic sanyo 25tqc22mv 22 25 7.3 4.3 3.1 poscap, 50m 16tqc100m 100 16 7.3 4.3 1.9 poscap, 45m 25svpf47m 47 25 6.6 6.6 5.9 os-con, 30m taiyo yuden umk325bj106mm-t 10 50 3.2 2.5 2.5 x5r ceramic tmk325bj226mm-t 22 25 3.2 2.5 2.5 x5r ceramic tdk ktj500b226m55bft00 22 50 6.0 5.3 5.5 x7r ceramic c5750x7r1h106m 10 50 5.7 5.0 2.0 x7r ceramic ckg57nx5r1e476m 47 25 6.5 5.5 5.5 x5r ceramic vishay 94svpd476x0035f12 47 35 10.3 10.3 12.6 os-con, 30m
ltc3115-1 20 31151f applications information programming custom input uvlo thresholds with the addition of an external resistor divider connected to the input voltage as shown in figure 4, the run pin can be used to program the input voltage at which the ltc3115-1 is enabled and disabled. for a rising input voltage, the ltc3115-1 is enabled when v in reaches the threshold given by the following equation, where r1 and r2 are the values of the resistor divider resistors: v th(rising) = 1.21v r1 + r2 r2 ? ? ? ? ? ? to ensure robust operation in the presence of noise, the run pin has two forms of hysteresis. a fixed 100mv of hysteresis within the run pin comparator provides a minimum run pin hysteresis equal to 8.3% of the input turn-on voltage independent of the resistor divider values. in addition, an internal hysteresis current that is sourced from the run pin during operation generates an additive level of hysteresis which can be programmed by the value of r1 to increase the overall hysteresis to suit the require - ments of specific applications. once the ic is enabled, it will remain enabled until the input voltage drops below the comparator threshold by the hysteresis voltage, v hyst , as given by the following equa - tion where r1 and r2 are values of the divider resistors: v hyst = r1 ? 0.5a + r1 + r2 r2 ? ? ? ? ? ? 0.1v therefore, the rising uvlo threshold and amount of hysteresis can be independently programmed via appro - priate selection of resistors r1 and r2. for high levels of hysteresis, the value of r1 can become larger than is desirable in a practical implementation (greater than 1m to 2m). in such cases, the amount of hysteresis can be increased further through the addition of an additional resistor, r h , as shown in figure 5. when using the additional r h resistor, the rising run pin threshold remains as given by the original equation and the hysteresis is given by the following expression: v hyst = r1 + r2 r2 ? ? ? ? ? ? 0.1v + r h r2 + r h r1 + r1r2 r2 0.5a ( ) figure 4. setting the input uvlo threshold and hysteresis figure 5. increasing input uvlo hysteresis ltc3115-1 gnd v in run r1 r2 31151 f04 ltc3115-1 gnd v in run r1 r h r2 3115 f05 to improve the noise robustness and accuracy of the uvlo thresholds, the run pin input can be filtered by adding a 1000pf capacitor from run to gnd. larger valued capaci - tors should not be utilized because they could interfere with operation of the hysteresis. bootstrapping the v cc regulator the high and low side gate drivers are powered through the pv cc rail which is generated from the input voltage through an internal linear regulator. in some applications, especially at higher operating frequencies and high input and output voltages, the power dissipation in the linear v cc regulator can become a key factor in the conversion efficiency of the converter and can even become a significant source of thermal heating. for example, at a 1.2mhz switching frequency, an input voltage of 36v, and an output voltage of 24v, the total pv cc /v cc current is approximately 18ma as shown in the typical performance characteristics section of this data sheet. as a result, this will generate 568mw of power dissipation in the v cc regulator which will result in an increase in die temperature of approximately 24 above ambient in the dfn package. this significant power loss will have a substantial impact on the conversion efficiency and the additional heating may limit the maximum ambient operating temperature for the application.
ltc3115-1 21 31151f applications information a significant performance advantage can be attained in applications which have the converter output voltage pro - grammed to 5v if the output voltage is utilized to power the pv cc and v cc rails. this can be done by connecting a schottky diode from v out to pv cc /v cc as shown in figure 6. with this bootstrap diode installed, the gate driver currents are generated directly by the buck-boost converter at high efficiency rather than through the internal linear regulator. to minimize current drawn from the output, the internal v cc regulator contains reverse blocking circuitry which minimizes the current into the pv cc /v cc pins when they are driven above the input voltage. the gain term, g buck , is comprised of three different components: the gain of the analog divider, the gain of the pulse width modulator, and the gain of the power stage as given by the following expressions where v in is the input voltage to the converter, f is the switching frequency, r is the load resistance, and t low is the switch pin minimum low time. curves showing the switch pin minimum low time can be found in the typical performance characteristics section of this data sheet. the parameter r s represents the average series resistance of the power stage and can be approximated as twice the average power switch re - sistance plus the dc resistance of the inductor. g buck = g divider g pwm g power g divider = 19.8 v in g pwm = 1.5 1? t low f ( ) g power = v in r 1? t low f ( ) r + r s ( ) notice that the gain of the analog divider cancels the input voltage dependence of the power stage. as a result, the buck mode gain is well approximated by a constant as given by the following equation: g buck = 29.7 r r + r s ? 29.7 = 29.5db the buck mode transfer function has a single zero which is generated by the esr of the output capacitor. the zero frequency, f z , is given by the following expression where r c and c o are the esr and value of the output filter ca - pacitor respectively. f z = 1 2 r c c o in most applications, an output capacitor with a very low esr is utilized in order to reduce the output voltage ripple to acceptable levels. such low values of capacitor esr result in a very high frequency zero and as a result the zero is commonly too high in frequency to significantly impact compensation of the feedback loop. figure 6. bootstrapping pv cc and v cc v out 4.7f 31151 f06 pv out ltc3115-1 v cc pv cc buck mode small-signal model the ltc3115-1 uses a voltage mode control loop to maintain regulation of the output voltage. an externally compensated error amplifier drives the vc pin to generate the appropriate duty cycle of the power switches. use of an external compensation network provides the flexibility for optimization of closed loop performance over the wide variety of output voltages, switching frequencies, and ex - ternal component values supported by the ltc3115-1. the small-signal transfer function of the buck-boost converter is different in the buck and boost modes of op - eration and care must be taken to ensure stability in both operating regions. when stepping down from a higher input voltage to a lower output voltage, the converter will operate in buck mode and the small-signal transfer function from the error amplifier output, v c , to the converter output voltage is given by the following equation: v o v c buck mode = g buck 1 + s 2 f z ? ? ? ? ? ? 1 + s 2 f o q + s 2 f o ? ? ? ? ? ? 2
ltc3115-1 22 31151f applications information the denominator of the buck mode transfer function ex - hibits a pair of resonant poles generated by the lc filtering of the power stage. the resonant frequency of the power stage, f o , is given by the following expression where l is the value of the inductor: f o = 1 2 r + r s lc o r + r c ( ) ? 1 2 1 lc o the quality factor, q, has a significant impact on compensa - tion of the voltage loop since a higher q factor produces a sharper loss of phase near the resonant frequency. the quality factor is inversely related to the amount of damping in the power stage and is substantially influenced by the average series resistance of the power stage, r s . lower values of r s will increase the q and result in a sharper loss of phase near the resonant frequency and will require more phase boost or lower bandwidth to maintain an adequate phase margin. q = lc o r + r c ( ) r + r s ( ) rr c c o + l + c o r s r + r c ( ) ? lc o l r + c o r s boost mode small-signal model when stepping up from a lower input voltage to a higher output voltage, the buck-boost converter will operate in boost mode where the small-signal transfer function from control voltage, v c , to the output voltage is given by the following expression. v o v c boost mode = g boost 1 + s 2 f z ? ? ? ? ? ? 1? s 2 f rhpz ? ? ? ? ? ? 1 + s 2 f o q + s 2 f o ? ? ? ? ? ? 2 in boost mode operation, the transfer function is character - ized by a pair of resonant poles and a zero generated by the esr of the output capacitor as in buck mode. however, in addition there is a right half plane zero which generates increasing gain and decreasing phase at higher frequen - cies. as a result, the crossover frequency in boost mode operation generally must be set lower than in buck mode in order to maintain sufficient phase margin. the boost mode gain, g boost , is comprised of three components: the analog divider, the pulse width modulator and the power stage. the gain of the analog divider and pwm remain the same as in buck mode operation, but the gain of the power stage in boost mode is given by the following equation: g power ? v out 2 1? t low f ( ) v in by combining the individual terms, the total gain in boost mode can be reduced to the following expression. notice that unlike in buck mode, the gain in boost mode is a function of both the input and output voltage. g boost ? 29.7v out 2 v in 2 in boost mode operation, the frequency of the right half plane zero, f rhpz , is given by the following expression. the frequency of the right half plane zero decreases at higher loads and with larger inductors. f rhpz = r 1? t low f ( ) 2 v in 2 2 l v out 2 in boost mode, the resonant frequency of the power stage has a dependence on the input and output voltage as shown by the following equation. f o = 1 2 r s + rv in 2 v out 2 lc o r + r c ( ) ? 1 2 ? v in v out 1 lc finally, the magnitude of the quality factor of the power stage in boost mode operation is given by the following expression. q = lc o r r s + rv in 2 v out 2 ? ? ? ? ? ? l + c o r s r
ltc3115-1 23 31151f applications information compensation of the voltage loop the small-signal models of the ltc3115-1 reveal that the transfer function from the error amplifier output, vc, to the output voltage is characterized by a set of resonant poles and a possible zero generated by the esr of the output capacitor as shown in the bode plot of figure 7. in boost mode operation, there is an additional right half plane zero that produces phase lag and increasing gain at higher frequencies. typically, the compensation network is designed to ensure that the loop crossover frequency is low enough that the phase loss from the right half plane zero is minimized. the low frequency gain in buck mode is a constant, but varies with both v in and v out in boost mode. in most applications, the low bandwidth of the type i com - pensated loop will not provide sufficient transient response performance. to obtain a wider bandwidth feedback loop, optimize the transient response, and minimize the size of the output capacitor, a type iii compensation network as shown in figure 9 is required. gain phase boost mode buck mode ?20db/dec ?40db/dec f o f 31151 f07 f rhpz 0 ?90 ?180 ?270 figure 7. buck-boost converter bode plot figure 8. error amplifier with type i compensation figure 9. error amplifier with type iii compensation for charging or other applications that do not require an optimized output voltage transient response, a simple type i compensation network as shown in figure 8 can be used to stabilize the voltage loop. to ensure sufficient phase margin, the gain of the error amplifier must be low enough that the resultant crossover frequency of the control loop is well below the resonant frequency. + ? c1 gnd ltc3115-1 vc 31151 f08 fb v out r bot r top 1000mv c fb r fb gnd ltc3115-1 vc 31151 f09 fb v out r bot r top r ff c ff 1000mv c pole + ? a bode plot of the typical type iii compensation network is shown in figure 10. the type iii compensation network provides a pole near the origin which produces a very high loop gain at dc to minimize any steady-state error in the regulation voltage. two zeros located at f zero1 and f zero2 provide sufficient phase boost to allow the loop crossover frequency to be set above the resonant frequency, f o , of the power stage. the type iii compensation network also introduces a second and third pole. the second pole, at frequency f pole2 , reduces the error amplifier gain to a zero slope to prevent the loop crossover from extending too high in frequency. the third pole at frequency f pole3 provides attenuation of high frequency switching noise.
ltc3115-1 24 31151f applications information the transfer function of the compensated type iii error amplifier from the input of the resistor divider to the output of the error amplifier, vc, is: v c (s) v out (s) = g ea 1 + s 2 f zero1 ? ? ? ? ? ? 1 + s 2 f zero2 ? ? ? ? ? ? s 1 + s 2 f pole1 ? ? ? ? ? ? 1 + s 2 f pole2 ? ? ? ? ? ? the error amplifier gain is given by the following equation. the simpler approximate value is sufficiently accurate in most cases since c fb is typically much larger in value than c pole . g ea = 1 r top c fb + c pole ( ) ? 1 r top c fb the pole and zero frequencies of the type iii compensation network can be calculated from the following equations where all frequencies are in hz, resistances are in ohms, and capacitances are in farads. f zero1 = 1 2 r fb c fb f zero2 = 1 2 r top + r ff ( ) c ff ? 1 2 r top c ff f pole2 = c fb + c pole 2 c fb c pole r fb ? 1 2 c pole r fb f pole3 = 1 2 c ff r ff in most applications the compensation network is designed so that the loop crossover frequency is above the resonant frequency of the power stage, but sufficiently below the boost mode right half plane zero to minimize the additional phase loss. once the crossover frequency is decided upon, the phase boost provided by the compensation network is centered at that point in order to maximize the phase margin. a larger separation in frequency between the zeros and higher order poles will provide a higher peak phase boost but may also increase the gain of the error amplifier which can push out the loop crossover to a higher frequency. the q of the power stage can have a significant influence on the design of the compensation network because it determines how rapidly the 180 of phase loss in the power stage occurs. for very low values of series resistance, r s , the q will be higher and the phase loss will occur sharply. in such cases, the phase of the power stage will fall rapidly to C180 above the resonant frequency and the total phase margin must be provided by the compensation network. however, with higher losses in the power stage (larger r s ) the q factor will be lower and the phase loss will occur more gradually. as a result, the power stage phase will not be as close to C180 at the crossover frequency and less phase boost is required of the compensation network. the ltc3115-1 error amplifier is designed to have a fixed maximum bandwidth in order to provide rejection of switching noise to prevent it from interfering with the control loop. from a frequency domain perspective, this can be viewed as an additional single pole as illustrated in figure 11. the nominal frequency of this pole is 300khz. for typical loop crossover frequencies below about 50khz the phase contributed by this additional pole is negligible. however, for loops with higher crossover frequencies this additional phase loss should be taken into account when designing the compensation network. figure 10. type iii compensation bode plot f zero1 phase 90 ?90 0 gain ?20db/dec ?20db/dec f zero2 31151 f10 f f pole2 f pole3 figure 11. internal loop filter + ? 1000mv fb ltc3115-1 vc r filt c filt 31151 f11 internal vc
ltc3115-1 25 31151f applications information loop compensation example this section provides an example illustrating the design of a compensation network for a typical ltc3115-1 applica - tion circuit. in this example a 5v regulated output voltage is generated with the ability to supply a 500ma load from an input power source ranging from 3.5v to 30v. to reduce switching losses a 750khz switching frequency has been chosen for this example. in this application the maximum inductor current ripple will occur at the highest input volt - age. an inductor value of 8.2h has been chosen to limit the worst-case inductor current ripple to approximately 600ma. a low esr output capacitor with a value of 20f is specified to yield a worst-case output voltage ripple (occurring at the worst-case step-up ratio and maximum load current) of approximately 12mv. in summary, the key power stage specifications for this ltc3115-1 example application are given below. f = 0.75mhz, t low = 0.1s v in = 3.5v to 30v v out = 5v at 500ma c out = 20f, r c = 10m l = 8.2h, r l = 45m with the power stage parameters specified, the compensa - tion network can be designed. in most applications, the most challenging compensation corner is boost mode operation at the greatest step-up ratio and highest load current since this generates the lowest frequency right half plane zero and results in the greatest phase loss. therefore, a reasonable approach is to design the compensation network at this worst-case corner and then verify that sufficient phase margin exists across all other operating conditions. in this example application, at v in = 3.5v and the full 500ma load current, the right half plane zero will be located at 70khz and this will be a dominant factor in determining the bandwidth of the control loop. the first step in designing the compensation network is to determine the target crossover frequency for the com - pensated loop. a reasonable starting point is to assume that the compensation network will generate a peak phase boost of approximately 60. therefore, in order to obtain a phase margin of 60, the loop crossover frequency, f c , should be selected as the frequency at which the phase of the buck-boost converter reaches C180. as a result, at the loop crossover frequency the total phase will be simply the 60 of phase provided by the error amplifier as shown: phase margin = buck-boost + erroramplifier + 180 = C180 + 60 + 180 = 60 similarly, if a phase margin of 45 is required, the target crossover frequency should be picked as the frequency at which the buck-boost converter phase reaches C195 so that the combined phase at the crossover frequency yields the desired 45 of phase margin. this example will be designed for a 60 phase margin to ensure adequate performance over parametric variations and varying operating conditions. as a result, the target crossover frequency, f c , will be the point at which the phase of the buck-boost converter reaches C180. it is generally difficult to determine this frequency analytically given that it is significantly impacted by the q factor of the resonance in the power stage. as a result, it is best determined from a bode plot of the buck-boost converter as shown in figure 12. this bode plot is for the ltc3115-1 buck-boost converter using the previously specified power stage parameters and was generated from the small-signal model equations using ltspice ? software. in this case, the phase reaches C180 at 24khz making f c = 24khz the target crossover frequency for the compensated loop. from the bode plot of figure 12 the gain of the power stage at the target crossover frequency is 19db. therefore, in order to make this frequency the crossover frequency in the compensated loop, the total loop gain at f c must be adjusted to 0db. to achieve this, the gain of the com - pensation network must be designed to be C19db at the crossover frequency.
ltc3115-1 26 31151f applications information the compensated error amplifier is determined simply by the amount of separation between the poles and zeros as shown by the following equation: max = 4 tan ?1 f p f z ? ? ? ? ? ? ? 270 a reasonable choice is to pick the frequency of the poles, f p , to be about 50 times higher than the frequency of the zeros, f z , which provides a peak phase boost of approxi - mately max = 60 as was assumed previously. next, the phase boost must be centered so that the peak phase occurs at the target crossover frequency. the frequency of the maximum phase boost, f center , is the geometric mean of the pole and zero frequencies as: f center = f p ? f z = 50 ? f z ? 7 ? f z therefore, in order to center the phase boost given a factor of 50 separation between the pole and zero frequencies, the zeros should be located at one seventh of the cross - over frequency and the poles should be located at seven times the crossover frequency as given by the following equations: f z = 1 7 ? f c = 1 7 24khz ( ) = 3.43khz f p = 7 ? f c = 7 24khz ( ) = 168khz this placement of the poles and zeros will yield a peak phase boost of 60 that is centered at the crossover frequency, f c . next, in order to produce the desired target crossover frequency, the gain of the compensation network at the point of maximum phase boost, g center , must be set to C19db. the gain of the compensated error amplifier at the point of maximum phase gain is given by: g center = 10log 2 f p 2 f z ( ) 3 r top c fb ( ) 2 ? ? ? ? ? ? ? ? db at this point in the design process, there are three con - straints that have been established for the compensation network. it must have C19db gain at f c = 24khz, a peak phase boost of 60 and the phase boost must be centered at f c = 24khz. one way to design a compensation network to meet these targets is to simulate the compensated error amplifier bode plot in ltspice for the typical compensation network shown on the front page of this data sheet. then, the gain, pole frequencies and zero frequencies can be iteratively adjusted until the required constraints are met. alternatively, an analytical approach can be used to design a compensation network with the desired phase boost, center frequency and gain. in general, this procedure can be cumbersome due to the large number of degrees of freedom in a type iii compensation network. however the design process can be simplified by assuming that both compensation zeros occur at the same frequency, f z , and both higher order poles (f pole2 and f pole3 ) occur at the common frequency, f p . in most cases this is a reasonable assumption since the zeros are typically located between 1khz and 10khz and the poles are typically located near each other at much higher frequencies. given this as - sumption, the maximum phase boost, f max , provided by figure 12. converter bode plot, v in = 3.5v, i load = 500ma frequency (hz) 10 gain (db) phase (deg) 0 10 20 10k 1m 31151 f12 ?10 ?20 ?30 100 1k 100k 30 40 50 ?200 ?160 ?120 ?240 ?280 ?320 ?80 ?40 0 gain phase f c
ltc3115-1 27 31151f applications information assuming a multiple of 50 separation between the pole frequencies and zero frequencies this can be simplified to the following expression: g center = 20log 50 2 f c r top c fb ? ? ? ? ? ? db this equation completes the set of constraints needed to determine the compensation component values. specifi- cally, the two zeros, f zero1 and f zero2 , should be located near 3.43khz. the two poles, f pole2 and f pole3 , should be located near 168khz and the gain should be set to provide a gain at the crossover frequency of g center = C19db. the first step in defining the compensation component values is to pick a value for r top that provides an acceptably low quiescent current through the resistor divider. a value of r top = 1m is a reasonable choice. next, the value of c fb can be found in order to set the error amplifier gain at the crossover frequency to C19db as follows: g center = ?19.1db = 20 log 50 2 24khz ( ) 1m ? ( ) c fb ? ? ? ? ? ? c fb = 50 2 24khz ( ) 1m ? ( ) a log ?19.1 20 ? ? ? ? ? ? ? 3.0nf the compensation poles can be set at 168khz and the zeros at 3.43khz by using the expressions for the pole and zero frequencies given in the previous section. setting the frequency of the first zero, f zero1 , to 3.43khz results in the following value for r fb : r fb = 1 2 3nf ( ) 3.43khz ( ) ? 15.4k ? this leaves the free parameter, c pole , to set the frequency f pole1 to the common pole frequency of 168khz as given: c pole = 1 2 15.4k ? ( ) 168khz ( ) ? 62pf next, c ff can be chosen to set the second zero, f zero2 , to the common zero frequency of 3.43khz. c ff = 1 2 1m ? ( ) 3.43khz ( ) ? 47pf finally, the resistor value r ff can be chosen to place the second pole at 168khz. r ff = 1 2 47pf ( ) 168hz ( ) ? 20.0k ? now that the pole frequencies, zero frequencies and gain of the compensation network have been established, the next step is to generate a bode plot for the compensated error amplifier to confirm its gain and phase properties. a bode plot of the error amplifier with the designed com - pensation component values is shown in figure 13. the bode plot confirms that the peak phase occurs at 24khz and the phase boost at that point is 57.7. in addition, the gain at the peak phase frequency is C19.3db which is close to the design target. frequency (hz) 10 ?40 gain (db) phase (deg) ?30 ?20 ?10 0 100 1k 10k 100k 3115 f13 1m 10 ?35 ?25 ?15 ?5 5 15 ?90 f c ?60 ?30 0 30 60 gain phase 90 figure 13. compensated error amplifier bode plot
ltc3115-1 28 31151f applications information the final step in the design process is to compute the bode plot for the entire loop using the designed compensation network and confirm its phase margin and crossover frequency. the complete loop bode plot for this example is shown in figure 14. the loop crossover frequency is 22khz which is close to the design target and the phase margin is approximately 60. the bode plot for the complete loop should be checked over all operating conditions and for variations in component values to ensure that sufficient phase margin exists in all cases. the stability of the loop should also be confirmed via time domain simulation and by evaluating the transient response of the converter in the actual circuit. output voltage programming the output voltage is set via the external resistor divider comprised of resistors r top and r bot as show in figures 8 and 9. the resistor divider values determine the output regulation voltage according to: v out = 1.000v 1 + r top r bot ? ? ? ? ? ? figure 14. complete loop bode plot frequency (hz) 10 ?60 gain (db) phase (deg) ?40 ?20 0 20 40 60 ?180 f c ?120 ?60 0 60 gain 120 180 100 1k 10k 100k 31151 f14 1m phase in addition to setting the output voltage, the value of r top is instrumental in controlling the dynamics of the compensation network. when changing the value of this resistor, care must be taken to understand the impact this will have on the compensation network. in addition, the thevenin equivalent resistance of the resistor divider controls the gain of the current limit. to maintain sufficient gain in this loop, it is recommended that the value of r top be chosen to be 1m or larger. switching frequency selection the switching frequency is set by the value of a resistor connected between the rt pin and ground. the switching frequency, f, is related to the resistor value by the following equation where r t is the resistance: f = 35.7mhz r t / k ? ( ) higher switching frequencies facilitate the use of smaller inductors as well as smaller input and output filter capaci - tors which results in a smaller solution size and reduced component height. however, higher switching frequencies also generally reduce conversion efficiency due to the increased switching losses. in addition, higher switching frequencies (above 750khz) will reduce the maximum output current that can be sup- plied (see typical performance characteristics for details). for applications with v out 20v, a maximum switching frequency of 1mhz is recommended.
ltc3115-1 29 31151f applications information pcb layout considerations the ltc3115-1 buck-boost converter switches large currents at high frequencies. special attention should be paid to the pc board layout to ensure a stable, noise-free and efficient application circuit. figures 15 and 16 show a representative pcb layout for each package option to outline some of the primary considerations. a few key guidelines are provided below: 1. the parasitic inductance and resistance of all circulat - ing high current paths should be minimized. this can be accomplished by keeping the routes to all bold components in figures 15 and 16 as short and as wide as possible. capacitor ground connections should via down to the ground plane by way of the shortest route possible. the bypass capacitors on pv in , pv out and pv cc /v cc should be placed as close to the ic as pos - sible and should have the shortest possible paths to ground. 2. the exposed pad is the electrical power ground connec - tion for the ltc3115-1 in the dhd package. multiple vias should connect the backpad directly to the ground plane. in addition, maximization of the metallization connected to the backpad will improve the thermal environment and improve the power handling capabilities of the ic in both the fe and dhd packages. 3. the components shown in bold and their connections should all be placed over a complete ground plane to minimize loop cross-sectional areas. this minimizes emi and reduces inductive drops. 4. connections to all of the components shown in bold should be made as wide as possible to reduce the series resistance. this will improve efficiency and maximize the output current capability of the buck-boost converter. 5. to prevent large circulating currents in the ground plane from disrupting operation of the ltc3115-1, all small-signal grounds should return directly to gnd by way of a dedicated kelvin route. this includes the ground connection for the rt pin resistor, and the ground connection for the feedback network as shown in figures 15 and 16. 6. keep the routes connecting to the high impedance, noise sensitive inputs fb and rt as short as possible to reduce noise pick-up. 7. the bst1 and bst2 pins transition at the switching frequency to the full input and output voltage respec - tively. to minimize radiated noise and coupling, keep the bst1 and bst2 routes as short as possible and away from all sensitive circuitry and pins (vc, fb, rt). in many applications the length of traces connecting to the boost capacitors can be minimized by placing the boost capacitors on the back side of the pc board and routing to them via traces on an internal copper layer.
ltc3115-1 30 31151f applications information figure 15. pcb layout recommended for the dhd package [16] pwm/ sync [15] sw1 via to ground plane (and to inner layer where shown) inner pcb layer routes v in uninterrupted ground plane should exist under all components shown in bold and under traces connecting to those components [14] pv in [13] bst1 c bst1 c bst2 [12] bst2 [17] pgnd [11] pv cc [10] v in [9] v cc 31151 f15 [2] sw2 [1] run [3] pv out [4] gnd [5] gnd r bot r top v out [6] vc kelvin back to gnd pin kelvin to v out [7] fb [8] rt r t
ltc3115-1 31 31151f applications information figure 16. pcb layout recommended for the fe package [19] pwm/ sync [18] sw1 [21] pgnd via to ground plane (and to inner layer where shown) inner pcb layer routes v in uninterrupted ground plane should exist under all components shown in bold and under traces connecting to those components [17] pv in [16] bst1 c bst1 c bst2 [15] bst2 [14] pv cc [13] v in [12] v cc 31151 f16 [3] sw2 [2] run [20] pgnd [1] pgnd [4] pv out [5] gnd [6] gnd r bot r top v out [7] vc kelvin back to gnd pin kelvin to v out [8] fb [9] rt [11] pgnd [10] pgnd r t
ltc3115-1 32 31151f typical applications wide input voltage range (2.7v to 40v), high efficiency 300khz, low noise 5v regulator bst1 bst2 pv in v in run pv out vc fb 27pf pv cc pwm/sync v cc rt sw1 sw2 gnd pgnd ltc3115-1 l1 33h d1 c bst1 0.1f c bst2 0.1f 2.7v to 40v c ff 82pf c1 4.7f 5v 1a v in > 3.6v 2a v in 6v c in 10f c o 330f r top 1m r bot 249k c in : murata grm55dr61h106k c o : poscap 6tpb330m (7.3mm 4.3mm 2.8mm) d1: panasonic ma785 l1: coilcraft mss1260 31151 ta02a r t 121k r ff 249k r fb 93.1k c fb 3300pf + pwm mode efficiency vs load current v out transient for a 0a to 2a load step, v in = 24v v out transient for a 0a to 1a load step load current (a) 0.01 70 efficiency (%) 75 80 85 90 0.1 1 31151 ta02b 65 60 55 50 95 100 v in = 5v v in = 3.6v v in = 2.7v pwm mode efficiency vs load current load current (a) 0.01 70 efficiency (%) 75 80 85 90 0.1 1 31151 ta02c 65 60 55 50 95 100 v in = 12v v in = 24v v in = 36v v out (200mv/div) v out (200mv/div) v out (200mv/div) v out (200mv/div) 2ms/div 31151 ta02d v in = 36v v in = 12v v in = 5v v in = 3.6v v out (200mv/div) inductor current (2a/div) load current (2a/div) 2ms/div 31151 ta02e
ltc3115-1 33 31151f typical applications wide input voltage range (10v to 40v) 1mhz 24v supply at 500ma maximum load current vs v in efficiency vs v in power-up/down waveforms, i load = 0.5a bst1 bst2 pv in v in run pv out vc fb pv cc pwm/sync v cc rt sw1 sw2 gnd pgnd ltc3115-1 l1 15h c bst1 0.1f c bst2 0.1f 10v to 40v uvlo programmed to 10v (1.3v hysteresis) c ff 22pf c1 4.7f 24v 500ma c in 10f c o 10f r top 1m r bot 43.2k l1: wrth 744 066 150 31151 ta03a r t 35.7k r1 953k r2 130k r ff 10k r fb 10k c fb 3300pf input voltage (v) 10 load current (a) 1.0 1.5 31151 ta03b 0.5 0 20 30 40 2.5 2.0 input voltage (v) 10 80 efficiency (%) 82 84 86 88 i load = 0.5a i load = 1a 92 20 30 31151 ta03c 40 90 v in (5v/div) v out (10v/div) inductor current (2a/div) 50ms/div 31151 ta03d
ltc3115-1 34 31151f typical applications industrial 12v 1mhz regulator with custom input undervoltage lockout thresholds pwm mode efficiency vs load current 0a to 1.5a load step, v in = 24v bst1 bst2 pv in v in run pv out vc fb pv cc pwm/sync v cc rt sw1 sw2 gnd pgnd ltc3115-1 l1 10h c bst1 0.1f c bst2 0.1f 10v to 40v c ff 33pf c1 4.7f 12v 1.4a c in 10f c o 22f r top 1m r bot 90.9k c in : murata grm55dr61h106k c o : tdk ckg57nx5r1h226m l1: wrth 744065100 31151 ta04a r t 35.7k r ff 10k r fb 40.2k c fb 820pf r1 2m r2 255k enabled when v in reaches 10.6v disabled when v in falls below 8.7v load current (a) 0.01 40 efficiency (%) 80 90 100 0.1 1 31151 ta04b 70 60 50 v in = 10.6v v in = 12v v in = 24v v in = 36v v out (500mv/div) inductor current (1a/div) 500s/div 31151 ta04c v out (500mv/div) inductor current (1a/div) 500s/div 31151 ta04d 0a to 1.5a load step, v in = 10.6v 0a to 1.5a load step, v in = 40v v out (500mv/div) inductor current (1a/div) 500s/div 31151 ta04e
ltc3115-1 35 31151f typical applications 24v 750khz industrial rail restorer regulated output voltage from a time varying input rail 0a to 1.5a load step, v in = 20v efficiency vs load current bst1 bst2 pv in v in run pv out vc fb rt pv cc v cc pwm/sync sw1 sw2 gnd pgnd ltc3115-1 l1 22h c bst1 0.1f c bst2 0.1f 20v to 40v open drain output c ff 47pf c1 4.7f 24v 1.5a c in 10f c o 82f 1f * r top 1m r bot 43.2k r t 47.5k c o : os-con 35svpf82m l1: toko 892nbs-220m *optional: install in applications subject to output overload or short-circuit conditions 31151 ta05a r ff 51k r fb 25k c fb 3300pf 100pf r1 500k + on off v in (5v/div) v out (5v/div) 10ms/div 31151 ta05b 40v 20v load current (1a/div) inductor current (2a/div) v out (1v/div) 500s/div 31151 ta05c load current (a) 0.01 60 efficiency (%) 80 100 0.10 1 31151 ta05d 40 50 70 90 30 20 v in = 20v v in = 24v v in = 36v
ltc3115-1 36 31151f typical applications usb, firewire, automotive and unregulated wall adapter to regulated 5v (750khz) efficiency vs load current, from automotive input soft-start waveform, v in = 24v, i load = 0.5a output voltage transient response, 750ma load step, powered from automotive input bst1 bst2 pv in v in 10f run pwm/sync pv out vc fb pv cc v cc rt sw1 sw2 gnd pgnd ltc3115-1 l1 10h d4 d3 d2 d1 c bst1 0.1f c bst2 0.1f usb 4.1v to 5.5v firewire 8v to 36v automotive 3.6v to 40v wall adapter 4v to 40v c ff 47pf c1 4.7f 5v 750ma c o 47f 2 r top 1m r bot 249k c in : murata grm55dr61h106k c o : grm43er60j476 d1-d4: b360a-13-f l1: coilcraft lps6225 31151 ta06a r t 47.5k r ff 51k r fb 100k c fb 4700pf burst pwm off on load current (a) 0.01 60 efficiency (%) 80 100 0.1 1 31151 ta06b 40 50 70 90 30 20 v in = 3.6v v in = 5v v in = 12v v in = 24v v in = 36v v out (200mv/div) v out (200mv/div) v out (200mv/div) 1ms/div 31151 ta06d v in = 36v v in = 12v v in = 3.6v v run (5v/div) v out (2v/div) v cc (5v/div) inductor current (500ma/div) 2ms/div 31151 ta06c
ltc3115-1 37 31151f typical applications miniature size 1.5mhz 12v supply load step transient response, 0ma to 500ma, v in = 6v load step transient response, 0ma to 500ma, v in = 24v efficiency vs load current, pwm mode efficiency vs load current, burst mode operation bst1 bst2 pv in v in run pv out vc burst pwm fb pv cc pwm/sync v cc rt sw1 sw2 gnd pgnd ltc3115-1 l1 4.7h c bst1 0.1f c bst2 0.1f 6v to 40v c ff 33pf 12v at 500ma 1a v in > 10v c1 4.7f c i 4.7f c o 10f r top 1m r bot 90.9k c o : murata grm55dr61h106k l1: wrth 7447789004 31151 ta07a r t 23.7k r ff 15k r fb 15k c fb 1000pf v out (500mv/div) inductor current (1a/div) load current (500ma/div) 200s/div 31151 ta07b v out (500mv/div) inductor current (1a/div) load current (500ma/div) 200s/div 31151 ta07c load current (a) 0.01 60 efficiency (%) 80 100 0.1 1 31151 ta07d 40 50 70 90 30 20 v in = 6v v in = 10v v in = 24v v in = 36v load current (ma) 0.1 60 efficiency (%) 70 80 90 1 10 100 31151 ta07e 50 40 30 20 v in = 6v v in = 10v v in = 24v v in = 36v
ltc3115-1 38 31151f dhd package 16-lead plastic dfn (5mm 4mm) (reference ltc dwg # 05-08-1707) 4.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjgd-2) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 2.44 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.34 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhd16) dfn 0504 0.25 0.05 pin 1 notch 0.50 bsc 4.34 0.05 (2 sides) recommended solder pad pitch and dimensions 2.44 0.05 (2 sides) 3.10 0.05 0.50 bsc 0.70 0.05 4.50 0.05 package outline 0.25 0.05 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3115-1 39 31151f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe20 (ca) tssop rev i 0211 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation ca
ltc3115-1 40 31151f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0312 ? printed in usa related parts typical application 750khz automotive 5v regulator with cold crank capability cold crank line transient with 1a load load dump line transient with 1a load efficiency vs load current v in = 12v bst1 bst2 pv in v in run pwm/sync pv out vc fb pv cc v cc rt sw1 sw2 gnd pgnd ltc3115-1 l1 6.8h c bst1 0.1f c bst2 0.1f automotive 3.6v to 40v c ff 33pf c1 4.7f 5v 1a c in 10f c o 47f r top 1m r bot 249k d1* c in : murata grm55dr61h106k c o : murata grm43er60j476k d1: panasonic ma785 l1: sumida cdrh8d43hpnp *optional-install d1 for improved efficiency and lower input operating voltage 31151 ta08a r t 47.5k r ff 42.2k r fb 54.9k c fb 1000pf burst pwm off on part number description comments LTC3112 2.5a (i out ), 15v synchronous buck-boost dc/dc converter v in : 2.7v to 15v, v out : 2.5v to 14v, i q = 40a, i sd < 1a, dfn and tssop packages ltc3113 3a (i out ), 2mhz synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 30a, isd < 1a, dfn and tssop packages ltc3127 1a (i out ), 1.2mhz buck-boost dc/dc converter with programmable input current limit 96% efficiency v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 35a, i sd < 4a, msop and dfn packages ltc3789 high efficiency, synchronous, 4-switch buck-boost controller v in : 4v to 38v, v out : 0.8v to 38v, i q = 3ma, i sd < 60a, ssop-28, qfn-28 packages ltc3785 10a (i out ), high efficiency, 1mhz synchronous, no r sense ? buck-boost controller v in : 2.7v to 10v, v out : 2.7v to 10v, i q = 86a, i sd < 15a, qfn package ltc3534 7v, 500ma (i out ), 1mhz synchronous buck-boost dc/dc converter 94% efficiency, v in : 2.4v to 7v, v out : 1.8v to 7v, i q = 25a, i sd < 1a, dfn and gn packages v in (2v/div) v out (200mv/div) inductor current (1a/div) 200ms/div 31151 ta08b 12v 6v 15ms fall time 4.5v v in (10v/div) v out (200mv/div) inductor current (1a/div) 2ms/div 31151 ta08c 40v 13.8v load current (a) 0.01 60 efficiency (%) 80 100 0.1 1 31151 ta08d 40 50 70 90 30 20 with bootstrap diode without bootstrap diode

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